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Added USB support

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This commit is contained in:
Daniel Fullmer 2020-11-21 17:04:57 -08:00
parent f29c04f775
commit 6e6cfc0d6f
2 changed files with 219 additions and 31 deletions
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5
README.md
View File

@ -1,7 +1,7 @@
# NixOS on Pinecube (Early work in progress)
Build an SD card image with `./build.sh`.
Prebuilt image [here](https://drive.google.com/file/d/1A3dreaxXnRpC_tdUey9V5ojnUXhLjLFd/view?usp=sharing) (last updated 2020-11-07).
Prebuilt image [here](https://drive.google.com/file/d/1iXVv9R-33DoFKE-WSPZ4XoemhYPZPcU2/view?usp=sharing) (last updated 2020-11-21).
Decompress and flash with:
```shell
$ cat ./result/sd-image/nixos-sd-image-21.03pre-git-armv7l-linux.img.zst | zstd -d | dd of=/dev/sdX bs=1024
@ -96,8 +96,7 @@ S3 datasheet says it supports up to 1000Mbit, but we only have a 100Mbit PHY: `H
Maybe this is for easier PoE support?
## USB
Not working in linux or u-boot.
dmesg reports: `supply vcc not found, using dummy regulator`
Working in linux, currently not in u-boot.
## WIFI
`iwlist wlan0 scan` worked fine.

245
kernel/Pine64-PineCube-support.patch
View File

@ -1,7 +1,7 @@
From 17bd28ff69e61f881d54cf4c606c04b55a43d478 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Wed, 23 Sep 2020 08:57:03 +0800
Subject: [PATCH 01/14] ARM: dts: sun8i: V3/V3s/S3/S3L: add Ethernet support
Subject: [PATCH 01/18] ARM: dts: sun8i: V3/V3s/S3/S3L: add Ethernet support
The Allwinner V3/V3s/S3L/SoChip S3 Ethernet MAC and internal PHY is quite
similar to the ones on Allwinner H3, except for V3s the external MII is
@ -110,13 +110,13 @@ index e5312869c0d2..b4069df84d10 100644
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>;
--
2.28.0
2.29.0
From c3e603b4fb67bcc5da7361c46c11f6101835d54c Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Wed, 23 Sep 2020 08:58:53 +0800
Subject: [PATCH 02/14] ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for UART2
Subject: [PATCH 02/18] ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for UART2
RX/TX
The UART2 RX/TX pins on Allwinner V3 series is at PB0/1, which is used
@ -155,13 +155,13 @@ index b4069df84d10..3932d227ac1c 100644
};
--
2.28.0
2.29.0
From ada1e0b448d8fd71eac999adbc3a179c0395002a Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Wed, 23 Sep 2020 08:58:54 +0800
Subject: [PATCH 03/14] ARM: dts: sun8i: V3/V3s/S3/S3L: add CSI1 device node
Subject: [PATCH 03/18] ARM: dts: sun8i: V3/V3s/S3/S3L: add CSI1 device node
The CSI1 controller of V3/V3s/S3/S3L chips is used for parallel CSI.
@ -196,13 +196,13 @@ index 3932d227ac1c..f221018d7cf3 100644
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
--
2.28.0
2.29.0
From 48cf51ab9126ea032f464157b2cf2a40f9a49be4 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Wed, 23 Sep 2020 09:00:11 +0800
Subject: [PATCH 04/14] ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for 8-bit
Subject: [PATCH 04/18] ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for 8-bit
parallel CSI
The CSI1 controller of V3/V3s/S3/S3L SoCs is used for parallel CSI.
@ -242,13 +242,13 @@ index f221018d7cf3..2727756bcd91 100644
pins = "PB6", "PB7";
function = "i2c0";
--
2.28.0
2.29.0
From e7b7e35f417676ac1e692730c16ab50f9d6e4da4 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Wed, 23 Sep 2020 09:00:12 +0800
Subject: [PATCH 05/14] ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for I2C1 at
Subject: [PATCH 05/18] ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for I2C1 at
PE bank
I2C1 controller is available at PE bank, usually used for
@ -279,13 +279,13 @@ index 2727756bcd91..3cd3b58c2587 100644
pins = "PB8", "PB9";
function = "uart0";
--
2.28.0
2.29.0
From 0ae37e2d02098a198f3d149b2e36b8e862a121ee Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Wed, 23 Sep 2020 09:02:14 +0800
Subject: [PATCH 06/14] dt-bindings: arm: sunxi: add Pine64 PineCube binding
Subject: [PATCH 06/18] dt-bindings: arm: sunxi: add Pine64 PineCube binding
Document board compatible names for Pine64 PineCube IP camera.
@ -311,13 +311,13 @@ index efc9118233b4..ba4a380ba4a3 100644
items:
- const: pine64,pine-h64
--
2.28.0
2.29.0
From 6dca04137361a821df34ef83b6f34fd1aa9fbb73 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Wed, 23 Sep 2020 09:02:15 +0800
Subject: [PATCH 07/14] ARM: dts: sun8i: s3l: add support for Pine64 PineCube
Subject: [PATCH 07/18] ARM: dts: sun8i: s3l: add support for Pine64 PineCube
IP camera
The Pine64 PineCube IP camera is an IP camera with SoChip S3 SoC.
@ -596,13 +596,13 @@ index 000000000000..9bab6b7f4014
+ status = "okay";
+};
--
2.28.0
2.29.0
From 7ad2976267f04f3b29327e470c9698bd689775d8 Mon Sep 17 00:00:00 2001
From: Daniel Fullmer <danielrf12@gmail.com>
Date: Fri, 23 Oct 2020 16:04:15 -0700
Subject: [PATCH 08/14] ARM: dts: sun8i: s3l: fix Pinecube IR LEDs
Subject: [PATCH 08/18] ARM: dts: sun8i: s3l: fix Pinecube IR LEDs
Signed-off-by: Daniel Fullmer <danielrf12@gmail.com>
---
@ -629,13 +629,13 @@ index 9bab6b7f4014..a4adf52ef406 100644
};
--
2.28.0
2.29.0
From 08043145ab7046e85339a9bd3221cc8ee53e64e5 Mon Sep 17 00:00:00 2001
From: Daniel Fullmer <danielrf12@gmail.com>
Date: Fri, 23 Oct 2020 16:05:10 -0700
Subject: [PATCH 09/14] ARM: dts: sun8i: s3l: add battery power supply to
Subject: [PATCH 09/18] ARM: dts: sun8i: s3l: add battery power supply to
pinecube
Signed-off-by: Daniel Fullmer <danielrf12@gmail.com>
@ -659,13 +659,13 @@ index a4adf52ef406..0319327dea3c 100644
regulator-always-on;
regulator-min-microvolt = <1250000>;
--
2.28.0
2.29.0
From 009e2c4615d99fcfe4fdaa8c1761afe649302a84 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.xyz>
Date: Wed, 24 May 2017 18:06:05 +0800
Subject: [PATCH 10/14] ARM: dts: sun8i: add DMA engine in V3s DTSI
Subject: [PATCH 10/18] ARM: dts: sun8i: add DMA engine in V3s DTSI
Allwinner V3s SoC features a DMA engine.
@ -698,13 +698,13 @@ index 3cd3b58c2587..4203a0964864 100644
compatible = "allwinner,sun8i-v3s-tcon";
reg = <0x01c0c000 0x1000>;
--
2.28.0
2.29.0
From 92cd60e77ba64615a6182f74e9bb23e2cb863100 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.xyz>
Date: Wed, 24 May 2017 18:06:06 +0800
Subject: [PATCH 11/14] ARM: dts: sun8i: add audio codec support into V3s DTSI
Subject: [PATCH 11/18] ARM: dts: sun8i: add audio codec support into V3s DTSI
Allwinner V3s SoC features an internal audio codec like the one in H3,
and a analog codec like the one in H3/A23 (but much simpler).
@ -768,13 +768,13 @@ index 4203a0964864..0a933c9dc779 100644
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
--
2.28.0
2.29.0
From c742763da8b136f1a62043531d5cf6c570732b0f Mon Sep 17 00:00:00 2001
From: Daniel Fullmer <danielrf12@gmail.com>
Date: Sat, 24 Oct 2020 15:13:51 -0700
Subject: [PATCH 12/14] ARM: dts: sun8i: s3l: enable audio on Pinecube
Subject: [PATCH 12/18] ARM: dts: sun8i: s3l: enable audio on Pinecube
TODO: Do this properly. Maybe add sun8i-s3-codec-analog
---
@ -819,13 +819,13 @@ index be872eefa61e..b806121abeeb 100644
static int sun8i_codec_analog_cmpnt_probe(struct snd_soc_component *cmpnt)
--
2.28.0
2.29.0
From 154d022acdfa415fbb1969ace6f74a21028fc9af Mon Sep 17 00:00:00 2001
From: microcai <microcaicai@gmail.com>
Date: Mon, 29 Jun 2020 23:36:40 +0800
Subject: [PATCH 13/14] spi-nor: Add support for xt25f32b/xt25f128b
Subject: [PATCH 13/18] spi-nor: Add support for xt25f32b/xt25f128b
The RockPi4b dev board ship with xt25f32b solded. add these ids so the
board's spi flash can be accessed within linux.
@ -903,13 +903,13 @@ index 000000000000..541fd8e52b79
+ .nparts = ARRAY_SIZE(xtx_parts),
+};
--
2.28.0
2.29.0
From 2c19e5196d862d18e65d990dc5c48d91a5a868d1 Mon Sep 17 00:00:00 2001
From: Daniel Fullmer <danielrf12@gmail.com>
Date: Sat, 24 Oct 2020 17:02:30 -0700
Subject: [PATCH 14/14] ARM: dts: sun8i: s3l: use flash for pinecube
Subject: [PATCH 14/18] ARM: dts: sun8i: s3l: use flash for pinecube
---
arch/arm/boot/dts/sun8i-s3-pinecube.dts | 2 +-
@ -929,5 +929,194 @@ index 35e501ec8073..edfa6847735c 100644
spi-max-frequency = <40000000>;
};
--
2.28.0
2.29.0
From 7a7f126557d5d4910b908cb83f39fdb294dbcd05 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Fri, 20 Nov 2020 13:08:51 +0800
Subject: [PATCH 15/18] ARM: dts: sun8i: v3s: fix GIC node memory range
Currently the GIC node in V3s DTSI follows some old DT examples, and
being broken. This leads a warning at boot.
Fix this.
Fixes: f989086ccbc6 ("ARM: dts: sunxi: add dtsi file for V3s SoC")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 0a933c9dc779..fe6339ad52b2 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -553,7 +553,7 @@ csi1: camera@1cb4000 {
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
+ <0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
--
2.29.0
From aa361de51f3d0909c8e4c1ee8f9374e98f72ac06 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Sun, 22 Nov 2020 08:38:39 +0800
Subject: [PATCH 16/18] ARM: dts: sun8i: v3s: add EHCI/OHCI0 device nodes
The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI
controllers.
Add the device nodes for the controllers.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index fe6339ad52b2..ea26fef67bfa 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -279,6 +279,25 @@ usbphy: phy@1c19400 {
#phy-cells = <1>;
};
+ ehci0: usb@1c1a000 {
+ compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
+ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
+ ohci0: usb@1c1a400 {
+ compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-v3s-ccu";
reg = <0x01c20000 0x400>;
--
2.29.0
From 65d891639488a741c2dfa3cdbeafae9a51634faa Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Sun, 22 Nov 2020 08:40:10 +0800
Subject: [PATCH 17/18] ARM: dts: sun8i: v3s: enable EHCI/OHCI for Lichee Pi
Zero
As the USB port on Lichee Pi Zero works in the OTG mode, enable the
EHCI/OHCI controllers for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
index 2e4587d26ce5..0cd969194acb 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
@@ -77,6 +77,10 @@ red_led {
};
};
+&ehci0 {
+ status = "okay";
+};
+
&mmc0 {
broken-cd;
bus-width = <4>;
@@ -84,6 +88,10 @@ &mmc0 {
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-0 = <&uart0_pb_pins>;
pinctrl-names = "default";
--
2.29.0
From ca1700b440f7c4bf6abdc3db8d598b3e8b7d2a31 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Sun, 22 Nov 2020 08:40:11 +0800
Subject: [PATCH 18/18] ARM: dts: sun8i: s3: switch PineCube to use OHCI/EHCI
only
The PineCube board features a USB Type-A connector connected to the
SoC's USB pins.
As this is not designed for being used as a USB device, disable OTG
controller and route USB to OHCI/EHCI fixedly.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm/boot/dts/sun8i-s3-pinecube.dts | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/sun8i-s3-pinecube.dts
index edfa6847735c..a852608e7666 100644
--- a/arch/arm/boot/dts/sun8i-s3-pinecube.dts
+++ b/arch/arm/boot/dts/sun8i-s3-pinecube.dts
@@ -78,6 +78,12 @@ csi1_ep: endpoint {
};
};
+&ehci0 {
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "okay";
+};
+
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
@@ -158,6 +164,12 @@ &mmc1 {
status = "okay";
};
+&ohci0 {
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "okay";
+};
+
&pio {
vcc-pd-supply = <&reg_dcdc3>;
vcc-pe-supply = <&reg_ldo3>;
@@ -228,11 +240,6 @@ &uart2 {
status = "okay";
};
-&usb_otg {
- dr_mode = "host";
- status = "okay";
-};
-
&usbphy {
usb0_vbus-supply = <&reg_vcc5v0>;
status = "okay";
--
2.29.0