diff --git a/README.md b/README.md index f07e742..a5316f8 100644 --- a/README.md +++ b/README.md @@ -67,7 +67,7 @@ $ cat /sys/class/gpio/gpio199/value dmesg error: `spi-nor spi0.0: unrecognized JEDEC id bytes: 0b 40 18 0b 40 18` ## Ethernet -Working fine in linux. U-boot needs support +Working fine in linux, and now also u-boot with patch derived from: https://lists.denx.de/pipermail/u-boot/2020-May/413924.html ## USB Not working in linux or u-boot diff --git a/configuration.nix b/configuration.nix index 8f68668..5b887ad 100644 --- a/configuration.nix +++ b/configuration.nix @@ -1,13 +1,7 @@ { config, lib, pkgs, ... }: let - uboot = pkgs.buildUBoot { - patches = [ ./0001-WIP-Initial-support-for-pinecube.patch ]; - - defconfig = "pinecube_defconfig"; - extraMeta.platforms = ["armv7l-linux"]; - filesToInstall = ["u-boot-sunxi-with-spl.bin"]; - }; + uboot = pkgs.callPackage ./uboot {}; in { imports = [ ]; diff --git a/0001-WIP-Initial-support-for-pinecube.patch b/uboot/0001-WIP-Initial-support-for-pinecube.patch similarity index 98% rename from 0001-WIP-Initial-support-for-pinecube.patch rename to uboot/0001-WIP-Initial-support-for-pinecube.patch index 6ecf955..b931983 100644 --- a/0001-WIP-Initial-support-for-pinecube.patch +++ b/uboot/0001-WIP-Initial-support-for-pinecube.patch @@ -1,7 +1,7 @@ From 9c657a26092f58815a7f68ede0bb6ef53bc0b5da Mon Sep 17 00:00:00 2001 From: Daniel Fullmer Date: Sat, 17 Oct 2020 13:05:16 -0700 -Subject: [PATCH] WIP Initial support for pinecube +Subject: [PATCH 1/3] WIP Initial support for pinecube --- arch/arm/dts/Makefile | 3 +- diff --git a/uboot/0002-sun8i-emac-sun8i-v3s-compatibility-for-sun8i-emac.patch b/uboot/0002-sun8i-emac-sun8i-v3s-compatibility-for-sun8i-emac.patch new file mode 100644 index 0000000..17ff9fa --- /dev/null +++ b/uboot/0002-sun8i-emac-sun8i-v3s-compatibility-for-sun8i-emac.patch @@ -0,0 +1,128 @@ +From 415ea55f47610b4181339e82ef310071b2c61340 Mon Sep 17 00:00:00 2001 +From: Daniel Fullmer +Date: Mon, 19 Oct 2020 22:50:57 -0700 +Subject: [PATCH 2/3] sun8i-emac: sun8i-v3s compatibility for sun8i-emac + +This patch expands the sun8i-emac driver to support the V3s. +For this the CLK and RST gates for EMAC and EPHY were added in clk_v3s.c + +Based on original patch by Benedikt-Alexander Mokru? +--- + drivers/clk/sunxi/clk_v3s.c | 6 ++++++ + drivers/net/sun8i_emac.c | 15 +++++++++++---- + 2 files changed, 17 insertions(+), 4 deletions(-) + +diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c +index b79446cc4f..5215d73e5e 100644 +--- a/drivers/clk/sunxi/clk_v3s.c ++++ b/drivers/clk/sunxi/clk_v3s.c +@@ -17,6 +17,7 @@ static struct ccu_clk_gate v3s_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), ++ [CLK_BUS_EMAC] = GATE(0x060, BIT(17)), + [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), + [CLK_BUS_OTG] = GATE(0x060, BIT(24)), + +@@ -24,6 +25,8 @@ static struct ccu_clk_gate v3s_gates[] = { + [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), + [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), + ++ [CLK_BUS_EPHY] = GATE(0x070, BIT(0)), ++ + [CLK_SPI0] = GATE(0x0a0, BIT(31)), + + [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), +@@ -35,12 +38,15 @@ static struct ccu_reset v3s_resets[] = { + [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), ++ [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)), + [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), + [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), + + [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), + [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), + [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), ++ ++ [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)), + }; + + static const struct ccu_desc v3s_ccu_desc = { +diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c +index e2b05ace8f..29d68d5c2d 100644 +--- a/drivers/net/sun8i_emac.c ++++ b/drivers/net/sun8i_emac.c +@@ -56,9 +56,11 @@ + #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) + + #define H3_EPHY_DEFAULT_VALUE 0x58000 ++#define V3S_EPHY_DEFAULT_VALUE 0x38000 + #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15) + #define H3_EPHY_ADDR_SHIFT 20 + #define REG_PHY_ADDR_MASK GENMASK(4, 0) ++#define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */ + #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ + #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ + #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ +@@ -112,6 +114,7 @@ enum emac_variant { + A64_EMAC, + R40_GMAC, + H6_EMAC, ++ V3S_EMAC, + }; + + struct emac_dma_desc { +@@ -279,10 +282,11 @@ static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg) + * needs to be configured and powered up before use + */ + *reg &= ~H3_EPHY_DEFAULT_MASK; +- *reg |= H3_EPHY_DEFAULT_VALUE; ++ *reg |= ((priv->variant == V3S_EMAC) ? V3S_EPHY_DEFAULT_VALUE : H3_EPHY_DEFAULT_VALUE); + *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT; + *reg &= ~H3_EPHY_SHUTDOWN; + *reg |= H3_EPHY_SELECT; ++ *reg |= H3_EPHY_CLK_SEL; + } else + /* This is to select External Gigabit PHY on + * the boards with H3 SoC. +@@ -311,7 +315,7 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, + + reg = readl(priv->sysctl_reg + 0x30); + +- if (priv->variant == H3_EMAC || priv->variant == H6_EMAC) { ++ if (priv->variant == H3_EMAC || priv->variant == H6_EMAC || priv->variant == V3S_EMAC) { + ret = sun8i_emac_set_syscon_ephy(priv, ®); + if (ret) + return ret; +@@ -320,7 +324,8 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, + reg &= ~(SC_ETCS_MASK | SC_EPIT); + if (priv->variant == H3_EMAC || + priv->variant == A64_EMAC || +- priv->variant == H6_EMAC) ++ priv->variant == H6_EMAC || ++ priv->variant == V3S_EMAC) + reg &= ~SC_RMII_EN; + + switch (priv->interface) { +@@ -985,7 +990,7 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) + return -EINVAL; + } + +- if (priv->variant == H3_EMAC) { ++ if (priv->variant == H3_EMAC || priv->variant == V3S_EMAC) { + ret = sun8i_get_ephy_nodes(priv); + if (ret) + return ret; +@@ -1038,6 +1043,8 @@ static const struct udevice_id sun8i_emac_eth_ids[] = { + .data = (uintptr_t)R40_GMAC }, + {.compatible = "allwinner,sun50i-h6-emac", + .data = (uintptr_t)H6_EMAC }, ++ {.compatible = "allwinner,sun8i-v3s-emac", ++ .data = (uintptr_t)V3S_EMAC }, + { } + }; + +-- +2.28.0 + diff --git a/uboot/0003-pinecube-Add-ethernet-support.patch b/uboot/0003-pinecube-Add-ethernet-support.patch new file mode 100644 index 0000000..d8f46f8 --- /dev/null +++ b/uboot/0003-pinecube-Add-ethernet-support.patch @@ -0,0 +1,120 @@ +From 876e12488bfd1ee18ad0f17d1cee09ba24bfab6a Mon Sep 17 00:00:00 2001 +From: Daniel Fullmer +Date: Tue, 20 Oct 2020 18:09:34 -0700 +Subject: [PATCH 3/3] pinecube: Add ethernet support + +--- + arch/arm/dts/sun8i-s3-pinecube.dts | 5 +++ + arch/arm/dts/sun8i-v3s.dtsi | 53 ++++++++++++++++++++++++++++++ + configs/pinecube_defconfig | 7 +--- + 3 files changed, 59 insertions(+), 6 deletions(-) + +diff --git a/arch/arm/dts/sun8i-s3-pinecube.dts b/arch/arm/dts/sun8i-s3-pinecube.dts +index d686b81894..16f9eea45b 100644 +--- a/arch/arm/dts/sun8i-s3-pinecube.dts ++++ b/arch/arm/dts/sun8i-s3-pinecube.dts +@@ -50,6 +50,7 @@ + compatible = "pine64,pinecube", "allwinner,sun8i-s3"; + + aliases { ++ ethernet0 = &emac; + serial0 = &uart0; + }; + +@@ -82,3 +83,7 @@ + usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; ++ ++&emac { ++ status = "okay"; ++}; +diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi +index ebefc0fefe..2a18ff0706 100644 +--- a/arch/arm/dts/sun8i-v3s.dtsi ++++ b/arch/arm/dts/sun8i-v3s.dtsi +@@ -96,6 +96,16 @@ + #size-cells = <1>; + ranges; + ++ syscon: system-control@1c00000 { ++ compatible = "allwinner,sun8i-v3s-system-control", ++ "allwinner,sun8i-h3-system-control"; ++ reg = <0x01c00000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++ ++ + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun7i-a20-mmc"; + reg = <0x01c0f000 0x1000>; +@@ -270,6 +280,49 @@ + status = "disabled"; + }; + ++ emac: ethernet@1c30000 { ++ compatible = "allwinner,sun8i-v3s-emac"; ++ syscon = <&syscon>; ++ reg = <0x01c30000 0x10000>; ++ interrupts = ; ++ interrupt-names = "macirq"; ++ resets = <&ccu RST_BUS_EMAC>; ++ reset-names = "stmmaceth"; ++ clocks = <&ccu CLK_BUS_EMAC>; ++ clock-names = "stmmaceth"; ++ phy-handle = <&int_mii_phy>; ++ phy-mode = "mii"; ++ status = "disabled"; ++ ++ mdio: mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "snps,dwmac-mdio"; ++ }; ++ ++ mdio_mux: mdio-mux { ++ compatible = "allwinner,sun8i-h3-mdio-mux"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ mdio-parent-bus = <&mdio>; ++ /* Only one MDIO is usable at the time */ ++ internal_mdio: mdio@1 { ++ compatible = "allwinner,sun8i-h3-mdio-internal"; ++ reg = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ int_mii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ clocks = <&ccu CLK_BUS_EPHY>; ++ resets = <&ccu RST_BUS_EPHY>; ++ }; ++ }; ++ }; ++ }; ++ + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, +diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig +index 361c187f12..ae71219296 100644 +--- a/configs/pinecube_defconfig ++++ b/configs/pinecube_defconfig +@@ -4,9 +4,4 @@ CONFIG_SPL=y + CONFIG_MACH_SUN8I_V3S=y + CONFIG_DRAM_CLK=360 + CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube" +-# CONFIG_NETDEVICES is not set +- +-# S3 uses DDR3 +-CONFIG_SUNXI_DRAM_DDR3_133=y +-CONFIG_SUNXI_DRAM_DDR2=n +-CONFIG_SUNXI_DRAM_DDR2_V3S=n ++CONFIG_SUN8I_EMAC=y +-- +2.28.0 +